Input and output delays describe the timing budget consumed outside your design module.
To establish a clock domain at an input port of the design, the create_clock command is utilized. This defines the period, waveform shape, and name of the clock.
check_timing : Run this after loading constraints. It flags unconstrained registers, loops, or missing clock definitions. synopsys timing constraints and optimization user guide 2021
report_analysis_coverage : Provides a high-level percentage score of how much of your design is meeting its timing requirements. Conclusion
Models clock jitter (inherent source variation) and clock skew (spatial distribution delay). Input and output delays describe the timing budget
Establish system frequency baselines and clock relationships. set_clock_uncertainty , set_clock_latency
The guide breaks down the two most critical checks: check_timing : Run this after loading constraints
: set_clock_groups identifies clocks as synchronous, asynchronous, or exclusive to prevent unnecessary timing analysis on unrelated paths. Optimization Strategies
: Constraining the external environment for the chip's ports.